SLAZ758A November   2024  – March 2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_05
    2. 6.2  ADC_ERR_06
    3. 6.3  ADC_ERR_07
    4. 6.4  ADC_ERR_08
    5. 6.5  CPU_ERR_01
    6. 6.6  CPU_ERR_02
    7. 6.7  FLASH_ERR_01
    8. 6.8  FLASH_ERR_02
    9. 6.9  I2C_ERR_05
    10. 6.10 PMCU_ERR_07
    11. 6.11 PMCU_ERR_10
    12. 6.12 PMCU_ERR_13
    13. 6.13 SPI_ERR_02
    14. 6.14 SPI_ERR_04
    15. 6.15 SPI_ERR_05
    16. 6.16 SPI_ERR_06
    17. 6.17 SPI_ERR_07
    18. 6.18 SRAM_ERR_01
    19. 6.19 SYSOSC_ERR_01
    20. 6.20 SYSOSC_ERR_02
    21. 6.21 TIMER_ERR_06
    22. 6.22 UART_ERR_01
    23. 6.23 UART_ERR_02
    24. 6.24 UART_ERR_04
    25. 6.25 UART_ERR_05
    26. 6.26 UART_ERR_06
    27. 6.27 UART_ERR_07
    28. 6.28 UART_ERR_08
  9. 7Trademarks
  10. 8Revision History

6.17 SPI_ERR_07

SPI Module

Category

Functional

Function

SPI underflow event may not generate if read/write to TXFIFO happen at the same time for SPI peripheral

Description

TXFIFO for SPI peripheral uses a bus synchronization scheme. While the control signal from BUSCLK domain to SPICLK domain is getting transferred, if read and write pointer points to the same head of FIFO, there is a possibility of data coherence issues. This issue only happens in corner case scenarios, and cause no underflow event being generated.

Workaround

Customer must ensure that TXFIFO on peripheral can never be empty when Controller is addressing the peripheral.
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